1. Field
Exemplary embodiments of the present invention relate to semiconductor designing technology, and more particularly, to an input/output strobe pulse control circuit for controlling input/output strobe pulses during a read operation, and a semiconductor memory device including the input/output strobe pulse control circuit.
2. Description of the Related Art
Semiconductor memory devices generally amplify cell data in a bit line sense amplifier during a read operation. The amplified cell data are transmitted from the bit line sense amplifier to an input/output sense amplifier through a pair of local input/output lines LIO/LIOB and then amplified again in the input/output sense amplifier to be outputted to an output unit through a global input/output line GIO.
Referring to FIG. 1, the column selection enable signal YI is enabled and data are loaded on the pair of the local input/output lines LIO/LIOB, individually. The input/output strobe pulse signal IOSTBP may be enabled when the voltage level difference between the local input/output lines LIO/LIOB becomes ΔV, and then the data may be transmitted from the local input/output lines LIO/LIOB to the global input/output line GIO. Subsequently, at the end of the enable section of the column selection enable signal YI, the local input/output lines LIO/LIOB that are developed may be precharged based on a local input/output line reset signal LIORST.
A delay time for outputting the input/output strobe pulse signal IOSTBP is decided based on a simulation result of the semiconductor memory device. However, to secure reliability under the actual operation conditions of the semiconductor memory device, the input/output strobe pulse signal IOSTBP is enabled by adding additional time to the delay time that is calculated through simulations. Also, since the time required to secure sensing margin varies depending on PVT conditions (Process, Voltage and Temperature), the moment when the input/output strobe pulse signal IOSTBP is enabled is set in consideration of the worst possible conditions. Although the input/output strobe pulse signal IOSTBP is delayed due to PVT conditions, the input/output strobe pulse signal IOSTBP gets sufficient time to be enabled within the enabling section of the column selection enable signal YI.
However, as the operation speed of semiconductor memory devices becomes higher and higher, clock frequencies become higher and higher, which narrows the enabling width of the column selection enable signal YI. If the input/output strobe pulse signal IOSTBP is delayed, the input/output strobe pulse signal IOSTBP may be enabled out of the enabling section of the column selection enable signal YI, which is shown in the dotted line in FIG. 1. When the input/output strobe pulse signal IOSTBP is enabled out of the enabling section of the column selection enable signal YI, the local input/output lines LIO/LIOB are precharged in response to the local input/output line reset signal LIORST and it becomes difficult to properly sense the data loaded on the local input/output lines LIO/LIOB.